Today's Editorial

Today's Editorial - 21 June 2024

India's semiconductor programme

Relevance: GS Paper III

Why in News? 

As the new coalition government returns to power with a reduced majority compared to its previous terms, there is curiosity about how the policies and incentives for the manufacturing push in the semiconductor field will evolve over the next five years.

More detail about news:

  • India announced a Rs 76,000 crore incentive package for semiconductors in December 2021. 
    • As of April, four projects have been approved under this scheme: 
    • Assembly, Testing, Marking and Packaging (ATMP) unit.
    • Outsourced Semiconductor Assembly and Test (OSAT) units, and one Silicon fab.
  • The approved projects include Micron's Rs 22,516 crore ATMP unit, Tata Semiconductor Assembly and Test (TSAT) Pvt Ltd's Rs 27,000 crore unit, CG Power's Rs 7,600 crore OSAT unit, and Tata Electronics Private Limited (TEPL)'s Rs 91,000 crore silicon fab unit. The total investment for these projects exceeds Rs 1.48 lakh-crore.
  • As of May, only about Rs 5,000 crore was left in the semiconductor package, indicating significant allocation of the initial funds. This includes incentives for 11 Design Linked Incentive (DLI) schemes approved so far.
  • The Micron approval faced criticism but was later clarified. It's a key part of the India-US iCET initiative, which aims to enhance cooperation. The Micron deal broke a multi-decade-long impasse for India, and notably, the three subsequent approved projects are led by Indian investors.

Goals and Challenges

  • India aims to achieve a 10% global market share in ATMP/OSAT within the next five years. This is an ambitious target given the competition from countries like China, Taiwan, South Korea, Japan, Malaysia, and Vietnam, which currently dominate the market.
  • The approved silicon fab by TEPL has a sanctioned capacity of about 50,000 wafer starts per month (wspm). It is expected to take 2-3 years for construction and equipment installation, and another 3-5 years to reach full capacity. By 2030-2032, when the TEPL fab is expected to be fully operational, it will contribute about 0.2% of the projected global semiconductor capacity.

Challenges and Future Considerations 

  • The focus is on the government's future allocations for silicon-based chip fab incentives and which commercial fab players will invest or transfer technology. Clear government priorities are crucial for private sector confidence.
  • Approving Tower Semiconductors' 65nm-40nm fab could boost India's market share and diversify into analog chips. If only 28nm or smaller nodes will be approved, this should be stated clearly to manage expectations. Powerchip's 28nm logic is still in development, with production expected in a few years.


The India Semiconductor Mission, the apex body overseeing the country's semiconductor initiatives, is yet to appoint a CEO or CTO, or staff with commercial semiconductor industry experience. This highlights the need for experienced leadership in driving India's semiconductor ambitions forward.

Beyond Editorial


  • The Initiative for Critical and Emerging Technology (iCET), launched in January 2023, represents a landmark agreement between India and the U.S on emerging technologies such as AI, semiconductors, biotech, and defense innovation. 
  • iCET is a significant development in the India-US relationship, as it elevates the two countries' strategic partnership to new heights. 
  • Some of the key focus Area:
    • Bridging our Innovation Ecosystems
    • Reaching New Heights in Civilian and Defense Space Technology Cooperation
    • Deepening Defense Innovation and Industrial Cooperation
    • Pursuing Advanced Telecommunications Opportunities
    • Combining Capabilities in Biotechnology and Biomanufacturing
    • Securing Semiconductor Supply Chains
    • Building a Clean Energy and a Critical Minerals Partnership for the 21st Century
    • Pursuing Quantum, Artificial Intelligence, and High-Performance Computing Collaboration

The Design Linked Incentive (DLI) Scheme

  • Semiconductors are at the heart of all electronic products and constitute a significant share in the Bill of Material (BOM). The National Policy on Electronics 2019 aims to position India as a global hub for Electronics System Design and Manufacturing (ESDM) and envisions creation of a vibrant semiconductor chip design ecosystem in the country. 
  • With an exceptional talent pool of 20% of world's semiconductor design engineers and thousands of chips designed by them every year in the country, India is poised for growth to achieve self-reliance and technology leadership in semiconductor design sector. 
  • Ministry of Electronics and Information technology has announced the Design Linked Incentive (DLI) Scheme to offset the disabilities in the domestic industry involved in semiconductor design in order to not only move up in value-chain but also strengthen the semiconductor chip design ecosystem in the country. 
  • CDAC is responsible for implementation of the DLI Scheme as Nodal Agency. The Design Linked Incentive (DLI) Scheme aims to offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor design(s) for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design(s) over a period of 5 years.

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